In conventional mobile wireless communication systems, especially Global System for Mobile Communications (“GSM”) cellular handsets, the transmit/receive (“T/R”) switch applied to the antenna end is capable of handling a high power signal of up to 35 dBm along with low harmonic distortion and low signal loss. The conventional mobile wireless communication systems further use a control voltage to actuate the switching wherein the control voltage is limited by the handset battery voltage, which in most conventional situations is about 3 volts and, in some cases, even less.
FIG. 1 illustrates a schematic diagram of a conventional single pole double throw (“SPDT”) field effect transistor (“FET”) switch for a receiver port 2 and a transmitter port 3 connected to an antenna port 1. When the control voltage Vcont1 for a receiver port 8, the receiver channel 8 providing the communication channel between the receiver port 2 and the antenna port 1, is 0.0 volts and the Vcont2 for a transmitter port 3, the transmitter channel 9 providing the communication channel between the transmitter port 3 and the antenna port 1, is 3.0 volts, the FET 5 of the receiver channel 8 is in an OFF state because the voltage drop between the gate G1 and the source S1 of FET 5 (VG1S1=VG1−VS1) in the FET 5 or the voltage drop between the gate G1 and the drain D1 of FET 5 (VG1D1=VG1−D1) in the FET 5 is below FET pinch-off voltage, VP.
While the FET 5 of the receiver channel 8 is in an OFF state, FET 4 of the transmitter channel 9 is in an ON state because the voltage drop between the gate G2 and the source S2 of FET 4 (VG2S2=VG2−VS2) in the FET 4 or the voltage drop between the gate G2 and the source D2 of FET 4 (VG2D2=VG2−VD2) in the FET 4 is above VP of FET 4.
When a high power RF signal passes through the ON-state FET 4 of the transmitter channel 9 to antenna port 1, it is also applied to the OFF-state FET 5 of the receiver channel 8 at the antenna port 1 as well. Due to extremely low resistance loss in FET 4, FET 4 remains in the ON state no matter how high a power is applied. Essentially, the power loss and generation of distortion are related to the change in operational status of FET 5. This can be verified through the simulation of the simplified small-signal equivalent circuit model of FET 5, as shown in FIG. 2.
Assuming that the RF signal is v=Vrf Sin(ωt), the voltage drop at each junction of FET 5 is expressed as below:VG1S1=VGS(DC)+(CGD1/(CGD1+CGS1))v  (1)VG1D1=VGD(DC)−(CGS1/(CGS1+CGS1))v  (2)where VGS(DC) and VGD(DC) are DC voltage drops in each junction in FET 5, respectively. Normally, VGD(DC)=VGS(DC) Vcont1−Vcont2=−3V; CGS1=CGD1 in a symmetrically designed FET 5; Vrf=17.8 V for a 35 dBm RF signal, and VP=−1.0 V which is a conventional pinch-off value in a HEMT design, thenVG1S1=−3+8.9·Sin(ωt)  (3)VG1D1=−3−8.9·Sin(ωt)  (4)
From Equations (3) and (4), it can be seen that VG1S1 is greater than VP, in a certain time period when v is in the positive half cycle, and VG1D1 is greater than VP, in a certain time period when v is in the negative half cycle. Therefore, FET 5 is not able to remain in the OFF state at all times, causing power loss and harmonic distortion.
The capability of power handling in a single FET switch can be estimated based on the drain current vs. gate-source voltage curve as illustrated in FIG. 3. The maximum power transfer without distortion is achieved by keeping FET 5 in OFF state. Hence,Vrf max=|Vcont1−Vcont2−VP|·((CGS1+CGD1)/CGD1)  (5)
So, the maximum power, Prf max, is obtained as demonstrated by Equation (6) below.Prf max=(1/2Z0)((CGS1+CGD1)/CGD1)2(Vcont1−Vcont2−VP)2  (6)where Z0 is the system impedance, normally equal to 50 Ω In a symmetric FET switch, Prfmax is calculated to be 22 dBm, which is much less than the specification for SPDT switches used in conventional cellular handset applications.
As seen from Equation (6), the lowering of the pinch-off voltage and/or the increasing of the control voltage can effectively improve power-handling capability and suppress harmonic distortion. However, the battery used in conventional cellular handset applications, as mentioned above, limits the control voltage. Moreover, the ON-state FET resistance Ron restricts VP. In other words, if the VP is lower, the insertion loss increases. Therefore, the lowering of the pinch-off voltage approach or the increasing of the control voltage approach are not viable candidates to effectively improve power-handling capability and suppress harmonic distortion due to the above-noted constraints.
Another conventional approach to increase power-handling capability is to use a plurality of FETs in series to replace single FET SPDT switches as shown in FIG. 4. As illustrated in FIG. 4, an antenna port 1 is connected to a receiver port 2 and a transmitter port 3 through a receiver channel 6 and a transmitter channel 7, respectively.
The receiver channel 6 includes three in series FETs (61, 62, and 63), each being connected to a control voltage source Vcont1. FET 61 has a source S1 (which is connected to the receiver port 2), a gate G1, and a drain D1. FET 62 has a source S2 (which is connected to the drain D1 of FET 61), a gate G2, and a drain D2. FET 63 has a source S3 (which is connected to the drain D2 of FET 62), a gate G3, and a drain D3 (which is connected to antenna port 1).
Likewise, the transmitter channel 7 includes three in series FET (71, 72, and 73), each being connected to a control voltage source Vcont2. FET 73 has a source S6 (which is connected to the transmitter port 3), a gate G6, and a drain D6. FET 72 has a source S5 (which is connected to the drain D6 of FET 73), a gate G5, and a drain D5. FET 71 has a source S4 (which is connected to the drain D5 of FET 72), a gate G4, and a drain D4 (which is connected to antenna port 1).
As explained above, the maximum transmit power with extremely low harmonic distortion can be derived based on the small signal equivalent circuit in FIG. 5.PRFmax=(9/2Z0)((CGS1+CGD1)/CGD1)2(Vcont1−Vcont2−VP)2  (7)where, assuming all three FETs are identical; i.e., CGS1=CGS2=CGS3=CGS and CGD1=CGD2=CGD3=CGD. Taking the parameters for a single FET, the maximum power PRFmax without distortion in three-FET switch can be calculated as 31.5 dBm according to Equation (7). Compared to the 22 dBm of PRFmax in the single FET switch analysis above, it clearly indicates that more FETs in series can improve power-handling capability of the switch. Thus, the PRFmax for “n” FETs in series can be easily deduced from Equation (7) as follows:PRFmax=(n2/2Z0)((CGS1+CGD1)/CGD1)2(Vcont1−Vcont2−VP)2  (8)The correlation of switch insertion loss in the transmitter branch and FET characteristics is written below.IL−20 log(1+(Ron/2Z0))  (9)RonnLG/(WG(Vcont1−Vcont2−VP))  (10)where IL is the insertion loss in dB, Ron is the total resistance of ON-state FETs in the transmitter branch, WG is the gate width of each FET, and LG is the gate length of each FET.
Equations (8) to (10) indicate that in a traditional SPDT switch, an increase of the number of FETs in series enhances the power handling capability and reduces signal distortion. On the other hand, the more FETs in series leads to a higher insertion loss. In addition, the increase of insertion loss caused by the reduction of VP, as mentioned above, is confirmed through the correlation of Ron and VP, in Equation (10).
Therefore, it is desirable to provide a SPDT switch with improved power-handling capability, low harmonic distortion, and low insertion loss that is not limited by the voltage of the battery being used in the cellular handset application, the pinch-off voltage of the FET used in the SPDT switch or the number of FETs in series in the SPDT switch.